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polyphase energy metering ic with pulsed output preliminary technical data ade7752b rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 analog devices, inc. all rights reserved. features high accuracy supports 50 hz/60 hz iec62053-21 less than 0.1% error over a dynamic range of 500 to 1 compatible with 3-phase 3-wire delta and 3-phase 4-wire wye configurations supplies average active power on the frequency outputs f1 and f2 high frequency output (cf) is intended for calibration and supplies instantaneous active power logic output revp indicates a potential miswiring or negative power on the sum of all phases direct drive for electromechanical counters and 2-phase stepper motors (f1 and f2) proprietary adcs and dsp provide high accuracy over large variations in environmental conditions and time on-chip power supply monitoring on-chip creep protection (no load threshold) based on the sum of the three phases on-chip reference 2.4 v 8% (25 ppm/c typical) with external overdrive capability single 5 v supply, low power (tbd mw typical) low cost cmos process general description the ade7752b 1 is an accurate active energy measurement ic intended for use in any 3-phase distribution system and has enhanced features that make it better suited for 3-phase 3-wire applications compared to the ade7752/52a. the no-load threshold and reverse polarity indication are based on the sum of the three phase energies in the ade7752b. the ade7752b specifications surpass the accuracy requirements as quoted in the iec62053-21 standard. the only analog circuitry used in the ade7752b is in the analog-to-digital converters (adcs) and reference circuit. all other signal processing (for example, multiplication, filtering, and summation) is carried out in the digital domain. this approach provides superior stability and accuracy over extremes in environmental conditions and over time. the ade7752b supplies average active power information on the low frequency outputs, f1 and f2. these logic outputs can be used to directly drive an electromechanical counter or to interface with an mcu. the cf logic output gives instantaneous active power information. this output is intended to be used for calibration purposes. the ade7752b includes a power supply monitoring circuit on the v dd pin. the ade7752b remains inactive until the supply voltage on v dd reaches 4 v. if the supply falls below 4 v, the ade7752b also resets and no pulses are issued on f1, f2, and cf. internal phase matching circuitry ensures that the voltage and current channels are phase matched. an internal no load threshold ensures the ade7752b does not exhibit any creep when there is no load. the ade7752b is available in a 24-lead soic package. 1 patent pending. functional block diagram 7 8 15 10 14 13 5 6 16 9 lpf hpf 3 clkout clkin dgnd cf s1 f1 f2 s0 scf revp digital-to-frequency converter 2.4v ref ref in/out agnd 4k ibp ibn vbp vn icp icn vcp iap ian va p adc adc adc adc v dd ade7752b power supply monitor adc adc phase correction phase correction phase correction 11 12 4 18 21 22 23 24 1 20 19 2 17 hpf hpf lpf lpf abs x x x 05905-001 figure 1.
ade7752b preliminary technical data rev. pra | page 2 of 27 table of contents features .............................................................................................. 1 general description ......................................................................... 1 table of contents .............................................................................. 2 specifications..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 9 terminology .................................................................................... 11 test circuit ...................................................................................... 12 theory of operation ...................................................................... 13 power factor considerations.................................................... 13 nonsinusoidal voltage and current ........................................ 14 analog inputs.................................................................................. 15 current channels ....................................................................... 15 voltage channels ........................................................................ 15 typical connection diagrams ...................................................... 16 current channel connection................................................... 16 voltage channels connection .................................................. 16 meter connections..................................................................... 16 power supply monitor ................................................................... 18 hpf and offset effects .................................................................. 19 digital-to-frequency conversion ................................................ 20 power measurement considerations....................................... 21 mode selection of the sum of the three active energies..... 21 transfer function ........................................................................... 22 frequency outputs f1 and f2 .................................................. 22 frequency output cf ................................................................ 23 selecting a frequency for an energy meter application........... 24 frequency outputs..................................................................... 24 no load threshold .................................................................... 24 negative power information..................................................... 25 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 26
preliminary technical data ade7752b rev. pra | page 3 of 27 specifications v dd = 5 v 5%, agnd = dgnd = 0 v, on-chip reference, clkin = 10 mhz, t min to t max = ?40c to +85c, unless otherwise noted. table 1. parameter conditions min typ max unit accuracy 1, 2 measurement error on current channel voltage channel with full-scale signal (500 mv), 25c, over a dynamic range of 500 to 1 0.1 % reading phase error between channels pf = 0.8 capacitive 0.1 degrees pf = 0.5 capacitive 0.1 degrees ac power supply rejection scf = 0, s0 = s1 = 1 output frequency variation (cf) ia = ib = ic = 100 mv rms, va = vb = vc = 100 mv rms @ 50 hz, ripple on v dd of 200 mv rms @ 100 hz 0.01 % reading dc power supply rejection s1 = 1; s0 = scf = 0 output frequency variation (cf) v1 = 100 mv rms, v2 = 100 mv rms, v dd = 5 v 250 mv 0.1 % reading analog inputs see analog inputs section maximum signal levels v ap C v n , v bp C v n , v cp C v n , i ap C i an , i bp C i bn , i cp C i cn 0.5 v peak difference input impedance (dc) clkin = 10 mhz 370 410 k bandwidth (?3 db) clkin/256, clkin = 10 mhz 14 khz adc offset error 1, 2 25 mv gain error external 2.5 v reference, ia = ib = ic = 500 mv dc 9 % ideal reference input ref in/out input voltage range 2.4 v + 8% 2.6 v 2.4 v ? 8% 2.2 v input impedance 3.3 k input capacitance 10 pf on-chip reference nominal 2.4 v reference error 200 mv temperature coefficient 25 ppm/c clkin all specifications for clkin of 10 mhz input clock frequency 10 mhz logic inputs 3 acf, s0, s1, and abs input high voltage, v inh v dd = 5 v 5% 2.4 v input low voltage, v inl v dd = 5 v 5% 0.8 v input current, i in typically 10 na, v in = 0 v to v dd 3 a input capacitance, c in 10 pf logic outputs 3 f1 and f2 output high voltage, v oh i source = 10 ma, v dd = 5 v 4.5 v output low voltage, v ol i sink = 10 ma, v dd = 5 v 0.5 v cf and negp output high voltage, v oh v dd = 5 v, i source = 5 ma 4.5 v output low voltage, v ol v dd = 5 v, i sink = 5 ma 0.5 v led_ctrl v dd = 5 v, clkin = 10 mhz output frequency 17.39 khz output high voltage v dd = 5 v, i source = 10 ma 4.5 v output low voltage v dd = 5 v, i sink = 10 ma tbd v
ade7752b preliminary technical data rev. pra | page 4 of 27 parameter conditions min typ max unit led_a, led_b, led_c output low i sink v dd = 4.75 v tbd ma output high source v dd = 4.75 v tbd ma power supply for specified performance v dd 5 v 5% 4.75 5.25 v i dd tbd tbd ma 1 see the terminology section for explanation of specifications. 2 see the plots in the typical performance characteristics section. 3 sample tested during initial release and after any redesign or process changes that might affect this parameter.
preliminary technical data ade7752b rev. pra | page 5 of 27 timing characteristics v dd = 5 v 5%, agnd = dgnd = 0 v, on-chip reference, clkin = 10 mhz, t min to t max = ?40c to +85c, unless otherwise noted. table 2. parameter 1,2 conditions specification unit t 1 3 f1 and f2 pulse width (logic high) 120 ms t 2 output pulse period (see the transfer function section) see figure 2 sec t 3 time between f1 falling edge and f2 falling edge 1/2 t 2 sec t 4 3, 4 cf pulse width (logic high) 90 ms t 5 5 cf pulse period (see the transfer function section) see table 7 sec t 6 minimum time between f1 and f2 pulse 4/clkin sec 1 sample tested during initial release and after any redesign or process changes that might affect this parameter. 2 see figure 2. 3 the pulse widths of f1, f2, and cf ar e not fixed for higher output frequencie s (see the frequency outputs section). 4 cf is not synchronous to f1 or f2 frequency outputs. 5 the cf pulse is always 1 s in the high frequency mode (see the frequency outputs section). f1 f2 cf t 1 t 6 t 2 t 3 t 4 t 5 05757-002 figure 2. timing diagram for frequency outputs
ade7752b preliminary technical data rev. pra | page 6 of 27 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to agnd ?0.3 v to +7 v v dd to dgnd ?0.3 v to +7 v analog input voltage to agnd va p, v b p, v c p, v n , i a p, i a n , i b p, i b n , i c p, and icn ?6 v to +6 v reference input voltage to agnd ?0.3 v to v dd + 0.3 v digital input voltage to dgnd ?0.3 v to v dd + 0.3 v digital output voltage to dgnd ?0.3 v to v dd + 0.3 v operating temperature range industrial ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c 28-lead soic, power dissipation 63 mw ja thermal impedance 55c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
preliminary technical data ade7752b rev. pra | page 7 of 27 pin configuration and function descriptions top view (not to scale) ade7752b ref in/out agnd icn icp ibn cf dgnd v dd revp ibp ian iap vn vcp vbp va p abs s0 f2 s1 f1 scf clkin clkout 2 3 4 5 6 7 8 9 10 11 12 124 23 22 21 20 19 18 17 16 15 14 13 05905-004 figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 cf calibration frequency logic output. the cf logic output gives instantaneous active power information. this output is intended to be used for calibration purposes. 2 dgnd this provides the ground reference for the digital ci rcuitry in the ade7752b, that is, multiplier, filters, and digital-to-frequency converter. because the digita l return currents in the ade7752b are small, it is acceptable to connect this pin to the an alog ground plane of the whole system. 3 v dd power supply. this pin provides the supply voltage for the digital circuitry in the ade7752b. the supply voltage should be maintained at 5 v 5% for specified operation. this pin should be decoupled to dgnd with a 10 f capacitor in parallel with a 100 nf ceramic capacitor. 4 revp this logic output goes logic high when negative power is detected on the sum of the three phase powers. this output is not latche d and resets when positive power is once again detected (see the negative power information section). 5, 6; 7, 8; 9, 10 iap, ian; ibp, ibn; icp, icn analog inputs for current channels. these channels are intended for use with current transducers and are referenced in this document as current channels . these inputs are fully differential voltage inputs with maximum differential input signal levels of 0 .5 v (see the analog inputs section). both inputs have internal esd protection circuitry; in addition, an overvoltage of 6 v can be sustained on these inputs without risk of permanent damage. 11 agnd this pin provides the ground reference for the analog circuitry in the ade7752b (adcs and reference). this pin should be tied to the anal og ground plane or the quietest gr ound reference in the system. this quiet ground reference should be used for all analog circuitry, such as, anti-aliasing filters and current and voltage transducers. to keep ground noise ar ound the ade7752b to a minimum, the quiet ground plane should only connect to the digital ground plane at one point. it is acceptable to place the entire device on the analog ground plane. 12 ref in/out this pin provides access to the on-chip voltage reference. the on-chip reference has a nominal value of 2.4 v 8% and a typical temperature coefficient of 25 ppm/c. an external reference source can also be connected at this pin. in either case, this pin should be decoupled to agnd with a 1 f ceramic capacitor. 13, 14, 15, 16 vn, vcp, vbp, vap analog inputs for the voltage channels. these channels are intended for use with voltage transducers and are referenced in this document as voltage cha nnels. these inputs are single-ended voltage inputs with a maximum signal level of 0.5 v with respect to vn for specified operation. all inputs have internal esd protection circuitry; in addition, an ov ervoltage of 6 v can be sustained on these inputs without risk of permanent damage. 17 abs this logic input is used to select the method by which the three active energies from each phase are summed. it selects between the arithmetical sum of the three energies (abs logic high) or the sum of the absolute values (abs logic low). see the mode selection of the sum of the three active energies section. 18 scf select calibration frequency. this logic input is us ed to select the frequency on the calibration output cf. table 7 shows how the calibration frequencies are selected. 19 clkin master clock for the adcs and digital signal processing . an external clock can be provided at this logic input. alternatively, a parallel resonant at crys tal can be connected across clkin and clkout to provide a clock source for the ade7752b. the clock frequency for the specified operation is 10 mhz. ceramic load capacitors between 22 pf and 33 pf should be used with the gate oscillator circuit. refer to the crystal manufacturers data sheet for the load capacitance requirements.
ade7752b preliminary technical data rev. pra | page 8 of 27 pin no. mnemonic description 20 clkout a crystal can be connected across this pin and clkin as described previously to provide a clock source for the ade7752b. the clkout pin can drive one cmos load when an external clock is supplied at clkin or when a crystal is being used. 21, 22 s0, s1 these logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion for design flexibility. 23, 24 f2, f1 low frequency logic outputs. f1 and f2 supply aver age active power information. the logic outputs can be used to drive electromechanical counters an d 2-phase stepper motors directly (see the transfer function section).
preliminary technical data ade7752b rev. pra | page 9 of 27 typical performance characteristics figure 4. error as a percent of reading with internal reference (wye connection) figure 5. error as a percent of reading over power factor with internal reference (wye connection) figure 6. error as a percent of reading over power factor with external reference (wye connection) figure 7. error as a percent of reading over temperature with internal reference (wye connection) figure 8. error as a percent of reading over power factor with internal referenc e (delta connection) figure 9. error as a percent of reading over temperature with external reference (wye connection)
ade7752b preliminary technical data rev. pra | page 10 of 27 figure 10. error as a percent of reading over frequency with an internal reference (wye connection) figure 11. error as a percent of reading over power supply with external reference (wye connection) figure 12. channel 1 offset distribution figure 13. error as a percent of reading over power supply with internal reference (wye connection)
preliminary technical data ade7752b rev. pra | page 11 of 27 terminology measurement error the error associated with the energy measurement made by the ade7752b is defined by the following formula: % ? 100 energy true energy true 7762 ade by registered energy error percentage ? ? ? ? ? ? = error between channels the high-pass filter (hpf) in the current channel has a phase lead response. to offset this phase response and equalize the phase response between channels, a phase correction network is placed in the current channel. the phase correction network ensures a phase match between the current channels and voltage channels to within 0.1 over a range of 45 hz to 65 hz and 0.2 over a range of 40 hz to 1 khz (see figure 25 and figure 26). power supply rejection (psr) this quantifies the ade7752b measurement error as a percentage of reading when the power supplies are varied. for the ac psr measurement, a reading at a nominal supply (5 v) is taken. a 200 mv rms/100 hz signal is then introduced onto the supply and a second reading is obtained under the same input signal levels. any error introduced is expressed as a percentage of reading. see definition for measurement error. for the dc psr measurement, a reading at nominal supplies (5 v) is taken. the supply is then varied 5% and a second reading is obtained with the same input signal levels. any error introduced is again expressed as a percentage of reading. adc offset error this refers to the dc offset associated with the analog inputs to the adcs. it means that with the analog inputs connected to agnd, the adcs still see an analog input signal offset. however, because the hpf is always present, the offset is removed from the current channel and the power calculation is not affected by this offset. gain error the gain error of the ade7752b is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. the difference is expressed as a percentage of the ideal frequency. the ideal frequency is obtained from the ade7752b transfer function (see the transfer function section).
ade7752b preliminary technical data rev. pra | page 12 of 27 test circuit v dd abs ref in/out 33nf 100nf 33nf 1k 1k 825 1k 10 f v dd vn agnd dgnd f1 3 17 f2 cf clkout clkin s0 s1 scf 10mhz 22pf 22pf ps2501-1 k7 k8 ade7752b v dd 1 24 23 to freq. counter 20 iap ian ibp ibn icp icn rb same as iap, ian same as iap, ian not connected same as vap revp 100nf 10 f vap vbp vcp 33nf 1k 1m 2 20 v 33nf 1k same as vap 5 6 7 8 9 10 16 15 14 13 11 4 12 18 22 21 19 2 i load 05905-015 figure 14. test circuit for performance curves
preliminary technical data ade7752b rev. pra | page 13 of 27 theory of operation the six signals from the current and voltage transducers are digitized with adcs. these adcs are 16-bit second-order - with an oversampling rate of 833 khz. this analog input structure greatly simplifies transducer interface by providing a wide dynamic range and bipolar input for direct connection to the transducer. high-pass filters in the current channels remove the dc component from the current signals. this eliminates any inaccuracies in the active power calculation due to offsets in the voltage or current signals (see the hpf and offset effects section). the active power calculation is derived from the instantaneous power signal. the instantaneous power signal is generated by a direct multiplication of the current and voltage signals of each phase. in order to extract the active power component, the dc component, the instantaneous power signal is low-pass filtered on each phase. figure 15 illustrates the instantaneous active power signal and shows how the active power information can be extracted by low-pass filtering the instantaneous power signal. this method is used to extract the active power information on each phase of the polyphase system. the total active power information is then obtained by adding the individual phase active power. this scheme correctly calculates active power for nonsinusoidal current and voltage waveforms at all power factors. all signal processing is carried out in the digital domain for superior stability over temperature and time. the low frequency output of the ade7752b is generated by accumulating the total active power information. this low frequency inherently means a long accumulation time between output pulses. the output frequency is therefore proportional to the average active power. this average active power information can, in turn, be accumulated (for example, by a counter) to generate active energy information. because of its high output frequency and therefore shorter integration time, the cf output is proportional to the instantaneous active power. this pulse is useful for system calibration purposes that would take place under steady load conditions. power factor considerations low-pass filtering, the method used to extract the active power information from the individual instantaneous power signal, is still valid when the voltage and current signals of each phase are not in phase. figure 16 displays the unity power factor condition and a displacement power factor (dpf) = 0.5, that is, current signal lagging the voltage by 60, for one phase of the polyphase. assuming that the voltage and current waveforms are sinusoidal, the active power component of the instantaneous power signal (the dc term) is given by () ? ? ? ? ? ? 60 cos 2 1 v (1) time iap ian vap hpf lpf ibp ibn vbp icp icn vcp vn digital-to- frequency digital-to- frequency f1 f2 cf instantaneous active power signal instantaneous power signal - p(t) instantaneous total power signal va ia + vb ib + vc ic 2 abs |x| lpf lpf |x| |x| p(t) = i(t) v(t) where: 2 {1+ cos (2 t)} v(t) = v cos ( t) i(t) = i cos ( t) p(t) = v i vi 2 vi v i 2 multiplier multiplier multiplier hpf hpf adc adc adc adc adc adc 05757-016 figure 15. signal processing block diagram
ade7752b preliminary technical data rev. pra | page 14 of 27 this is the correct active power calculation. instantaneous active power signal instantaneous power signal instantaneous active power signal instantaneous power signal v i 2 cos(60 ) v i 2 60 current current voltage voltage 0v 0v 05757-017 figure 16. dc component of instantaneous power signal nonsinusoidal voltage and current the active power calculation method also holds true for non- sinusoidal current and voltage waveforms. all voltage and current waveforms in practical applications have some harmonic content. using the fourier transform, instantaneous voltage and current waveforms can be expressed in terms of their harmonic content () () n n n o t n v v t v + + = = sin 2 0 (2) where: v ( t ) is the instantaneous voltage. v o is the average value. v n is the rms value of voltage harmonic n . and n is the phase angle of the voltage harmonic. () () n n n o t n i v i t i + = = sin 2 0 (3) where: i ( t ) is the instantaneous current. i o is the dc component. i n is the rms value of current harmonic n . n is the phase angle of the current harmonic. using equations 2 and 3, the active power, p , can be expressed in terms of its fundamental active power ( p 1 ) and harmonic active power ( p h ). p = p 1 + p h where: 1 1 1 1 1 1 1 cos ? = = i v p (4) n n n n n n h n i v p ? = = = cos 1 (5) as can be seen from equation 5, a harmonic active power component is generated for every harmonic, provided that harmonic is present in both the voltage and current waveforms. the power factor calculation has been shown to be accurate in the case of a pure sinusoid. therefore, the harmonic active power also correctly accounts for power factor since harmonics are made up of a series of pure sinusoids. a limiting factor on harmonic measurement is the bandwidth. on the ade7752b, the bandwidth of the active power measurement is 14 khz with a master clock frequency of 10 mhz.
preliminary technical data ade7752b rev. pra | page 15 of 27 analog inputs current channels the voltage outputs from the current transducers are connected to the ade7752b current channels, which are fully differential voltage inputs. iap, ibp, and icp are the positive inputs for ian, ibn, and icn, respectively. the maximum peak differential signal on the current channel should be less than 500 mv (353 mv rms for a pure sinusoidal signal) for the specified operation. differential input 500mv max peak +500mv agnd v cm ia iap v cm ?500mv common-mode 25mv max ian iap?ian 05757-018 figure 17. maximum signal levels, current channel the maximum signal levels on iap and ian are shown in figure 17. the maximum differential voltage between iap and ian is 500 mv. the differential voltage signal on the inputs must be referenced to a common mode, for example, agnd. the maximum common-mode signal shown in figure 17 is 25 mv. voltage channels the output of the line voltage transducer is connected to the ade7752b at this analog input. voltage channels are a pseudo- differential voltage input. vap, vbp, and vcp are the positive inputs with respect to vn. the maximum peak differential signal on the voltage channel is 500 mv (353 mv rms for a pure sinusoidal signal) for speci- fied operation. figure 18 illustrates the maximum signal levels that can be connected to the ade7752b voltage channels. differential input 500mv max peak +500mv agnd vcm va va p v cm ?500mv common-mode 25mv max vn v a p?vn 05757-019 figure 18. maximum signal levels, voltage channel voltage channels must be driven from a common-mode voltage, that is, the differential voltage signal on the input must be refer- enced to a common mode (usually agnd). the analog inputs of the ade7752b can be driven with common-mode voltages of up to 25 mv with respect to agnd. however, best results are achieved using a common mode equal to agnd.
ade7752b preliminary technical data rev. pra | page 16 of 27 typical connection diagrams current channel connection figure 19 shows a typical connection diagram for the current channel (ia). a current transformer (ct) is the current trans- ducer selected for this example. notice the common-mode voltage for the current channel is agnd and is derived by center tapping the burden resistor to agnd. this provides the complementary analog input signals for iap and ian. the ct turns ratio and burden resistor rb are selected to give a peak differential voltage of 500 mv at maximum load. in theory it is better to center tap rb; however, this requires very careful attention to the layout and matching of the resistors to ensure that the channels have the same resistance. a single resistor may be more practical and is a valid design choice. iap 500mv r b rf rf ct neutral phase ip ian cf cf 05757-020 figure 19. typical connection for current channels voltage channels connection figure 20 shows two typical connections for the voltage chan- nel. the first option uses a potential transformer (pt) to pro- vide complete isolation from the main voltage. in the second option, the ade7752b is biased around the neutral wire, and a resistor divider is used to provide a voltage signal proportional to the line voltage. adjusting the ratio of ra, rb, and vr is a convenient way of carrying out a gain calibration on the meter. vr can be implemented using either a potentiometer or a binary weighted series of resistors. either configuration works, however, the potentiometer is subject to noise over time. two fixed value resistors can be used in place of vr to minimize the noise. 500mv ra * rb * vr * vap agnd rf rf pt neutral phase vn cf cf vap rf neutral phase vn cf cf * ra >> rf + vr; * rb + vr = rf 05757-021 500mv figure 20. typical connections for voltage channels meter connections in 3-phase service, two main power distribution services exist: 3-phase 4-wire or 3-phase 3-wire. the additional wire in the 3-phase 4-wire arrangement is the neutral wire. the voltage lines have a phase difference of 120 (2/3 radians) between each other (see equation 6). () ( ) () () ? ? ? ? ? ? + = ? ? ? ? ? ? + = = 3 4 cos 2 3 2 cos 2 cos 2 t v t v t v t v t v t v l c c l b b l a a (6) where v a , v b , and v c represent the voltage rms values of the different phases. the current inputs are represented by () ( ) () () ? ? ? ? ? ? + + = ? ? ? ? ? ? + + = + = c l c c b l b b a l a a t i t i t i t i t i t i 3 4 cos 2 3 2 cos 2 cos 2 (7) where: i a , i b , and i c represent the rms value of the current of each phase. a , b , and c represent the phase difference of the current and voltage channel of each phase. the instantaneous powers can then be calculated as follows: p a (t) = v a (t) i a (t) p b (t) = v b (t) i b (t) p c (t) = v c (t) i c (t) then: ( ) ( ) ( ) () () () () ? ? ? ? ? ? + + ? = ? ? ? ? ? ? + + ? = + ? = c l c c c c c c b l b b b b b b a l a a a a a a t i v i v t p t i v i v t p t i v i v t p 3 8 2 cos cos 3 4 2 cos cos 2 cos cos (8) as shown in equation 8, in the ade7752b, the active power calculation per phase is made when current and voltage inputs of one phase are connected to the same channel (a, b, or c). then the summation of each individual active power calcula- tion gives the total active power information, p ( t ) = p a ( t ) + p b ( t ) + p c ( t ).
preliminary technical data ade7752b rev. pra | page 17 of 27 figure 21 shows the connections of the ade7752b analog inputs with the power lines in a 3-phase 3-wire delta service. ct rb* antialiasing filters iap ian source rb* ra* rb* vr* rf cf cf vn ra* vr* cf load phase a phase b phase c ct rb* vap vbp antialiasing filters ibn ibp * ra >> rf + vr; * rb + vr = rf 05757-022 figure 21. 3-phase 3-wire meter connection with ade7752b note that only two current inputs and two voltage inputs of the ade7752b are used in this case. the active power calculated by the ade7752b does not depend on the selected channels. figure 22 shows the connections of the ade7752b analog inputs with the power lines in a 3-phase 4-wire wye service. source icp icn load ct ibp ibn antialiasing filters phase a phase b phase c rb* ra* vr* cf va p ct rb* antialiasing filters iap ian ct rb* antialiasing filters rb* ra* vr* cf vcp rf cf vn rb* ra* vr* cf vbp rb* * ra >> rf + vr; * rb + vr = rf 05757-023 figure 22. 3-phase 4-wire meter connection with ade7752b
ade7752b preliminary technical data rev. pra | page 18 of 27 power supply monitor the ade7752b contains an on-chip power supply monitor. the power supply (v dd ) is monitored continuously by the ade7752b. at power up, when the supply is less than 4v 2% and v ref is less than 1.9 v (typ), the outputs of the ade7752b are inactive and the data path is held in reset. once v dd is greater than 4v 2% and v ref is greater than 1.9 v (typ), the chip is active and energy accumulation begins. at power-down, when v dd falls below 4 v or v ref falls below 1.9 v (typ), the data path is again held in reset. this implementation ensures correct device operation at power- up and at power-down. the power supply monitor has built-in hysteresis and filtering. this gives a high degree of immunity to false triggering due to noisy supplies. the power supply and decoupling for the part should be such that the ripple at v dd does not exceed 5% as specified for normal operation. v dd v ref 5v 4v 0v internal reset active inactive 05757-024 2.4v 1.9v inactive figure 23. on-chip power supply monitor
ade7752b preliminary technical data rev. pra | page 19 of 27 hpf and offset effects figure 24 shows the effect of offsets on the active power calculation. an offset on the current channel and voltage channel contributes a dc component after multiplication as shown in figure 24. since this dc component is extracted by the lpf and is used to generate the active power information for each phase, the offsets can contribute a constant error to the total active power calculation. the hpf in the current channels avoids this problem easily. by removing the offset from at least one channel, no error component can be generated at dc by the multiplication. error terms at cos(t) are removed by the lpf and the digital-to-frequency conversion (see the digital-to- frequency conversion) section. () {} () {} () () () t i v t v i t i v i v i v i t i v t v os os os os os os + + + + = + + 2 cos 2 cos cos 2 cos cos (9) v os i os i os v v os i dc component (including error term) is extracted by the lpf for real power calculat ion 2 frequency ? rad/s 2 v i 0 05757-026 figure 24. effect of channel offset on the active power calculation the hpf in the current channels has an associated phase response that is compensated for on-chip. figure 25 and figure 26 show the phase error between channels with the compensation network. the ade7752b is phase compensated up to 1 khz as shown. this ensures correct active harmonic power calculation even at low power factors. figure 25. phase error between channels (0 hz to 1 khz) figure 26. phase error between channels (40 hz to 70 hz)
ade7752b preliminary technical data rev. pra | page 20 of 27 digital-to-frequency conversion after multiplication, the digital output of the low-pass filter contains the active power information of each phase. however, since this lpf is not an ideal brick wall filter implementation, the output signal also contains attenuated components at the line frequency and its harmonics, that is , cos(ht), where h = 1, 2, 3 . the magnitude response of the filter is given by () 2 8 1 1 | | ? ? ? ? ? ? + = f f h (10) where the ?3 db cutoff frequency of the low-pass filter is 8 hz. for a line frequency of 50 hz, this would give an attenuation of the 2(100 hz) component of approximately ?22 db. the dominating harmonic is twice the line frequency, that is, cos(2t), due to the instantaneous power signal. figure 27 shows the instantaneous active power signal at the output of the cf, which still contains a significant amount of instantaneous power information, cos(2 t). this signal is then passed to the digital-to-frequency converter where it is integrated (accumulated) over time to produce an output frequency. this accumulation of the signal suppresses or averages out any non-dc component in the instantaneous active power signal. the average value of a sinusoidal signal is zero. thus, the frequency generated by the ade7752b is proportional to the average active power. figure 27 shows the digital-to-frequency conversion for steady load conditions, that is, constant voltage and current. the frequency output cf varies over time, even under steady load conditions (see figure 27). this frequency variation is primarily due to the cos(2t) components in the instantaneous active power signal. the output frequency on cf can be up to 160 higher than the frequency on f1 and f2. the higher output frequency is generated by accumulating the instantaneous active power signal over a much shorter time, while converting it to a frequency. this shorter accumulation period means less averaging of the cos(2t) component. therefore, some of this instantaneous power signal passes through the digital-to-frequency conversion. where cf is used for calibration purposes, the frequency counter should average the frequency to remove the ripple and obtain a stable frequency. if cf is being used to measure energy, for example, in a microprocessor-based application, the cf output should also be averaged to calculate power. because the outputs f1 and f2 operate at a much lower frequency, significant averaging of the instantaneous active power signal is carried out. the result is a greatly attenuated sinusoidal content and a virtually ripple-free frequency output on f1 and f2, which are used to measure energy in a stepper-motor based meter. lpf to extract real power (dc term) multiplier lpf multiplier lpf multiplier lpf digital-to- frequency digital-to- frequency f1 f2 cf va ia vb ib vc ic frequency cf frequency time f1 cos(2 t) attenuated by lpf 2 frequency ? rad/s 2 v i 0 instantaneous real power signal (frequency domain) |x| |x| |x| abs time 05757-029 figure 27. active power-to-frequency conversion
preliminary technical data ade7752b rev. pra | page 21 of 27 power measurement considerations calculating and displaying power information always have some associated ripple that depends on the integration period used in the mcu to determine average power as well as the load. for example, at light loads, the output frequency can be 10 hz. with an integra- tion period of two seconds, only about 20 pulses are counted. the possibility of missing one pulse always exists since the ade7752b output frequency is running asynchronously to the mcu timer. this would result in a 1-in-20 or 5% error in the power measure- ment. to remedy this, an appropriate integration time should be considered to achieve the desired accuracy. mode selection of the sum of the three active energies the ade7752b can be configured to execute the arithmetic sum of the three active energies, wh = wh a + wh b + wh c , or the sum of the absolute value of these energies, wh = |wh a | + |wh b | + |wh c |. the selection between the two modes can be made by setting the abs pin. logic high and logic low applied on the abs pin correspond to the arithmetic sum and the sum of absolute values, respectively. when the sum of the absolute values is selected, the active energy from each phase is always counted positive in the total active energy. it is particularly useful in 3-phase 4-wire instillation where the sign of the active power should always be the same. if the meter is misconnected to the power lines, that is, ct connected in the wrong direction then the total active energy recorded without this solution can be reduced by two- thirds. the sum of the absolute values assures that the active energy recorded represents the actual active energy delivered. regardless of the mode selected using this pin, the reverse power pin still detects when negative power is present on the sum of the three phase inputs.
ade7752b preliminary technical data rev. pra | page 22 of 27 transfer function frequency outputs f1 and f2 the ade7752b calculates the product of six voltage signals (on current channel and voltage channel) and then low-pass filters this product to extract active power information. this active power information is then converted to a frequency. the frequency information is output on f1 and f2 in the form of active high pulses. the pulse rate at these outputs is relatively low, for example, 2.01 hz maximum for ac signals with scf = s0 = 0; s1 = 1 (see table 6). this means that the frequency at these outputs is generated from active power information accumulated over a relatively long period. the result is an output frequency that is proportional to the average active power. the averaging of the active power signal is implicit to the digital-to-frequency conversion. the output frequency or pulse rate is related to the input voltage signals by the following equation: () 2 ref 7 1 c cn b bn a an v f i v i v i v 181 . 6 freq ? + + = (11) where: freq = output frequency on f1 and f2 (hz). v an, v bn, and v cn = differential rms voltage signal on voltage channels (v). i a , i b , and i c = differential rms voltage signal on current channels (v). v ref = the reference voltage (2.4 v 8%) (v). f 1C7 = one of seven possible frequencies selected by using the logic inputs scf, s0, and s1 (see table 5). table 5. f 1C7 frequency selection 1 scf s1 s0 f 1C7 (hz) 0 0 0 2.30 1 0 0 4.61 0 0 1 1.15 1 0 1 4.61 0 1 0 5.22 1 1 0 1.15 0 1 1 0.58 1 1 1 0.58 1 f 1C7 is a fraction of the master clock and therefore varies if the specified clkin frequency is altered. example 1 thus, if full-scale differential dc voltages of +500 mv are applied to va, vb, vc, ia, ib, and ic, respectively (500 mv is the maximum differential voltage that can be connected to current and voltage channels), then the expected output frequency is calculated as follows: f 1C7 = 0.58 hz, scf = s0 = s1 = 1 v an = v bn = v cn = ia = ib = ic = 500 mv dc = 0.5 v(rms of dc = dc) v ref = 2.4 v (nominal reference value) note that if the on-chip reference is used, actual output frequencies can vary from device to device due to reference tolerance of 8%. hz 467 . 0 4 . 2 58 . 0 5 . 0 5 . 0 181 . 6 3 freq 2 = = (12) example 2 in this example, with ac voltages of 500 mv peak applied to the voltage channels and current channels, the expected output frequency is calculated as follows: () value reference nominal v 4 . 2 v vrms 2 5 . 0 ac peak mv 500 ic ib ia v v v 1 1 s 0 s scf , hz 58 . 0 f ref cn bn an 7 1 = = = = = = = = = = = = ? (13) note that if the on-chip reference is used, actual output fre- quencies can vary from device to device due to reference tolerance of 8%. hz 233 . 0 4 . 2 2 2 58 . 0 5 . 0 5 . 0 181 . 6 3 freq 2 = = (14) as can be seen from these two example calculations, the maximum output frequency for ac inputs is always half of that for dc input signals. the maximum frequency also depends on the number of phases connected to the ade7752b. in a 3-phase 3-wire delta ser- vice, the maximum output frequency is different from the maxi- mum output frequency in a 3-phase 4-wire wye service. the reason is that there are only two phases connected to the analog inputs, but also that in a delta service, the current channel input and voltage channel input of the same phase are not in phase in normal operation.
preliminary technical data ade7752b rev. pra | page 23 of 27 example 3 in this example, the ade7752b is connected to a 3-phase 3- wire delta service as shown in figure 21. the total active energy calculation processed in the ade7752b can be expressed as total ac tive power = ( v a C v c ) i a + ( v b C v c ) i b where: v a , v b , and v c represent the voltage on phase a, phase b, and phase c, respectively. i a and i b represent the current on phase a and phase b, respectively. as the voltage and current inputs respect equations 5 and 6, the total active power ( p ) is () ( ) ( ) ( ) () () ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? ? ? ? ? + ? = ? ? + ? ? = 3 2 cos 2 3 4 cos 2 3 2 cos 2 cos 2 3 4 cos 2 cos 2 t i t v v t v t i t v t v p ibn ibp vc vb ian iap vc va p l b l c l b l a l c l a (15) for simplification, assume that a = b = c = 0 and v a = v b = v c = v . the preceding equation becomes () () ? ? ? ? ? ? + + ? ? ? ? ? ? + ? ? ? ? ? ? + ? ? ? ? ? ? = 3 2 cos sin 3 sin 2 cos 3 2 sin 3 2 sin 2 t t i v t t i v p l l b l l a (16) p then becomes ? ? ? ? ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? = 3 2 sin 3 sin 3 2 2 sin 3 2 sin t i vbn t i van p l b l a (17) where: van = v sin(2/3). vbn = v sin(/3). as the lpf on each channel eliminates the 2 l component of the equation, the active power measured by the ade7752b is 2 3 2 3 + = b bn a an i v i v p (18) if full-scale ac voltage of 500 mv peak is applied to the voltage channels and current channels, the expected output frequency is calculated as follows: value reference nominal v 4 . 2 v 0 ic v rms v 2 5 . 0 ac peak v m 500 ic ib ia v v 1 1 s 0 s scf , hz 60 . 0 f ref cn bn an 7 1 = = = = = = = = = = = = = ? (19) note that if the on-chip reference is used, actual output frequencies can vary from device to device due to reference tolerance of 8%. hz 139 . 0 2 3 4 . 2 2 2 60 . 0 5 . 0 5 . 0 181 . 6 2 freq 2 = = (20) table 6 shows a complete listing of all maximum output frequencies when using all three channel inputs. table 6: maximum output frequency on f1 and f2 scf s1 s0 maximum frequency for ac inputs (hz) maximum frequency for dc inputs (hz) 0 0 0 0.93 1.85 1 0 1 1.86 3.71 0 0 1 0.46 0.93 1 0 1 1.86 3.71 0 1 0 2.10 4.20 1 1 0 0.46 0.93 0 1 1 0.23 0.47 1 1 1 0.23 0.47 frequency output cf the pulse output calibration frequency (cf) is intended for use during calibration. the output pulse rate on cf can be up to 64 the pulse rate on f1 and f2. table 7 shows how the two frequencies are related, depending on the states of the logic inputs s0, s1, and scf. because of its relatively high pulse rate, the frequency at this logic output is proportional to the instantaneous active power. as is the case with f1 and f2, the frequency is derived from the output of the low-pass filter after multiplication. however, since the output frequency is high, this active power information is accumulated over a much shorter time. thus, less averaging is carried out in the digital-to- frequency conversion. the cf output is much more responsive to power fluctuations with much less averaging of the active power signal (see figure 15). table 7. maximum output frequency on cf scf s1 s0 f 1C7 (hz) cf maximum for ac signals (hz) 0 0 0 2.3 16 f1, f2 = 14.88 1 0 0 4.61 8 f1, f2 = 14.88 0 0 1 1.15 32 f1, f2 = 14.88 1 0 1 4.61 16 f1, f2 = 29.76 0 1 0 5.22 160 f1, f2 = 336 1 1 0 1.15 16 f1, f2 = 7.36 0 1 1 0.58 32 f1, f2 = 7.36 1 1 1 0.58 16 f1, f2 = 3.68
preliminary technical data ade7752b rev. pra | page 24 of 27 selecting a frequency for an energy meter application as shown in table 5, the user can select one of seven frequencies. this frequency selection determines the maximum frequency on f1 and f2. these outputs are intended to be used to drive the energy register (electromechanical or other). since seven different output frequencies can be selected, the available frequency selection has been optimized for a 3-phase 4-wire service with a meter constant of 100 imp/kwhr and a maximum current of between 10 a and 100 a. table 8 shows the output frequency for several maximum currents (i max ) with a line voltage of 220 v (phase neutral). in all cases, the meter constant is 100 imp/kwhr. table 8. f1 and f2 frequency at 100 imp/kwhr i max (a) f1 and f2 (hz) 10 0.18 25 0.46 40 0.73 60 1.10 80 1.47 100 1.83 the f 1C7 frequencies allow complete coverage of this range of output frequencies on f1 and f2. when designing an energy meter, the nominal design voltage on the voltage channels should be set to half scale to allow for calibration of the meter constant. the current channel should also be no more than half scale when the meter sees maximum load. this allows overcurrent signals and signals with high crest factors to be accommodated. table 9 shows the output frequency on f1 and f2 when all six analog inputs are half scale. table 9. f1 and f2 frequency with half-scale ac inputs scf s1 s0 f 1C7 (hz) frequency on f1 and f2 (half-scale ac inputs) (hz) 0 0 0 2.3 0.23 1 0 0 4.61 0.46 0 0 1 1.15 0.12 1 0 1 4.61 0.46 0 1 0 5.22 0.53 1 1 0 1.15 0.12 0 1 1 0.58 0.06 1 1 1 0.58 0.06 when selecting a suitable f 1C7 frequency for a meter design, the frequency output at i max (maximum load) with a 100 imp/kwhr meter constant should be compared with column 5 of table 9. the frequency that is closest in table 9 determines the best choice of frequency (f 1C7 ). for example, if a 3-phase 4-wire wye meter with a 25 a maximum current is being designed, the output frequency on f1 and f2 with a 100 imp/kwhr meter constant is 0.46 hz at 25 a and 220 v (see table 8). looking at table 9, the closest frequency to 0.46 hz in column 5 is 0.53 hz. therefore, f 1C7 = 5.22 hz is selected for this design. frequency outputs figure 2 shows a timing diagram for the various frequency outputs. the outputs f1 and f2 are the low frequency outputs that can be used to directly drive a stepper motor or electro- mechanical impulse counter. the f1 and f2 outputs provide two alternating high going pulses. the pulse width (t 1 ) is set at 120 ms, and the time between the rising edges of f1 and f2 (t 3 ) is approximately half the period of f1 (t 2 ). if, however, the period of f1 and f2 falls below 550 ms (1.81 hz), the pulse width of f1 and f2 is set to half of their period. the maximum output frequencies for f1 and f2 are shown in table 6. the high frequency cf output is intended to be used for communications and calibration purposes. cf produces a 90 ms- wide active high pulse (t 4 ) at a frequency proportional to active power. the cf output frequencies are given in table 7. as in the case of f1 and f2, if the period of cf (t 5 ) falls below 190 ms, the cf pulse width is set to half the period. for example, if the cf frequency is 20 hz, the cf pulse width is 25 ms. no load threshold the ade7752b includes no load threshold and start-up current circuitry features that eliminate any creep effects in the meter. the circuit is designed to issue a minimum output frequency. any load generating a frequency lower than this minimum output frequency does not cause a pulse to be issued on f1, f2, or cf. the no-load threshold is determined by the sum of all phases. the minimum output frequency is given as 0.0075% of the full- scale output frequency for each of the f 1C7 frequency selections, or approximately 0.0029% of the f 1C7 frequency (see table 10). for example, for an energy meter with a 100 imp/kwhr meter constant using f 1C7 (4.61 hz), the minimum output frequency at f1 or f2 would be 13.35 10 C5 hz. this would be 2.13 10 C3 hz at cf (16 f1 hz). in this example, the no load threshold would be equivalent to 4.8 w of load or a start-up current of 20.03 ma at 240 v.
preliminary technical data ade7752b rev. pra | page 25 of 27 table 10. cf, f1, and f2 minimum frequency at no load threshold scf s1 s0 f1, f2 minimum (hz) cf minimum (hz) 0 0 0 6.94e ? 05 1.11e ? 03 1 0 0 1.39e ? 04 1.11e ? 03 0 0 1 3.47e ? 05 1.11e ? 03 1 0 1 1.39e ? 04 2.23e ? 03 0 1 0 1.58e ? 04 2.52e ? 02 1 1 0 3.47e ? 05 5.55e ? 04 0 1 1 1.75e ? 05 5.60e ? 04 1 1 1 1.75e ? 05 2.80e ? 04 negative power information the ade7752b detects when total power, calculated as the sum of the three phases, is negative. this mechanism can detect an incorrect connection of the meter or generation of negative active energy. the revp pin output goes active high when negative power is detected on the sum of the three phase inputs. if positive active power is detected on the sum of three phases, then revp pin output is low. the revp pin output changes state at the same time as a pulse is issued on cf. if the sum of the phases measure negative power, then the revp pin output stays high until the sum of the phases measures positive power.
ade7752b preliminary technical data rev. pra | page 26 of 27 outline dimensions compliant to jedec standards ms-013-ad 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.020) 0.31 (0.012) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 24 13 12 1 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 15.60 (0.6142) 15.20 (0.5984) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. figure 28. 24-lead standard small outline package [soic_w] wide body (rw-24) dimensions shown in millimeters and (inches) ordering guide model package description package option ade7752barwz 1 28-lead standard small outline package [soic_w] rw-28 2 ADE7752BARWZ-RL 1 28-lead standard small outline package [soic_w] rw-28 on 13" reels ade7752barw 28-lead standard small outline package [soic_w] rw-28 ade7752barw-rl 28-lead standard small outline package [soic_w] rw-28 on 13" reels eval-ade7752beb ade7752b evaluation board 1 z = pb-free part. 2 rw = small outline wide body package in tubes.
preliminary technical data ade7752b rev. pra | page 27 of 27 notes ? 2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr05905-0-1/06(pra)

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